Circuit designs can be debugged in a number of different ways. One way is to simulate a circuit design within a register transfer level (RTL) simulator. An RTL simulator provides a high degree of visibility into the circuit design. Typically, the behavior of nearly any circuit element and/or signal may be observed. RTL simulators, however, operate at slow simulation speeds. That is, the speed at which simulation of the circuit design is performed is typically much slower than the speed at which the physical circuit would operate once implemented within an integrated circuit device (IC).
Another type of debugging technique involves including one or more probe points within a circuit design. The circuit design can be processed (e.g., placed and routed), and implemented within an IC (e.g., within a programmable IC such as a programmable logic device). The probe points are then implemented at specified locations within the IC and embedded in the device under test (DUT), e.g., the circuit design. The probe points can sample information from within the DUT and provide that information to a memory, a controller, or to a location or component off-chip. A benefit of this technique is that the IC runs at full speed.
When testing speed is increased, however, visibility into the DUT decreases. Each probe point requires resources of the IC that, once used by a probe point, are unavailable for use by the circuit design. Further, a signal path must be established for each probe point. This requires routing resources. Any routing resources used by a probe point also are unavailable for use by the circuit design. Effectively, the probe points compete with the DUT for resources of the IC. This typically limits the number of probe points that may be used.
In view of the complexity of modern circuit designs and the limited availability of probe points, it is unlikely that a probe point will be located at each location within the DUT that is desirable. Typically, as more information is gathered to identify the source of a circuit error, it becomes necessary to move one or more probe points to another location within the DUT, e.g., closer to the source of the error, to obtain more useful information. In most cases, moving a probe point requires that the circuit design undergo full placement and routing. This can take a significant amount of time.
In other cases, probe points may be moved and routes modified without full placement and routing. In such cases, care must be taken when re-routing signals so as not to disturb high frequency signals or other areas in which logic is densely packed.